1. Field of the Invention
The present invention relates to a transmission system, in particular to a clock signal converting apparatus of the transmission system.
2. Background of the Related Art
FIG. 1 is a block diagram of a related art clock signal converting apparatus of a transmission system. As shown therein, a first clock signal generator 10 is a working unit and a second clock signal generator 20 is a protection unit. Each of the first and second clock signal generators 10, 20 generates a system clock signal SCLK, a multi-frame pulse MFP, and a frame pulse FP containing frame information, which are provided to a system 30. The system 30 performs synchronization of other signals based on inputted signals SCLK, MFP, and FP.
FIG. 2 is a block diagram of the first and second clock signal generators 10, 20 of FIG. 1. As depicted in FIG. 2, the first clock signal generator 10 comprises a Phase Locked Loop (PLL) control unit 11 for controlling a PLL, and a Voltage Controlled Oscillator (VCO) 12 for outputting a reference clock signal in accordance with an output signal of the PLL control unit 11. The first clock signal generator 10 further includes a signal generating circuit 13 for generating the system clock signal SCLK and the system signals MFP, FP based on the reference clock signal outputted from the VCO 12, and a buffer 14 for temporarily storing the signals MFP, FP, and SCLK outputted from the signal generating circuit 13. The buffer 14 outputs the signals in accordance with a converting control signal ACT. The second clock signal generator 20 has the same construction as the first clock signal generator 10, but has different reference numerals. Additionally, the second clock signal generator 20 includes an inverter, which receives and forwards the converting control signal ACT to the buffer 24.
In operation, the first and second clock signal generators 10, 20 generate the system clock signal SCLK, the multi-frame pulse MFP, and the frame pulse FP in accordance with the reference clock signal of a whole system, and provide these signals to the system 30.
As depicted in FIG. 2, the VCO 12 generates the reference clock signal in accordance with the control of the PLL control unit 11. The signal generating circuit 13 is provided with the standard clock signal, generates the system clock signal SCLK and the system signals MFP, FP, and provides them to the buffer 14.
As depicted in FIG. 3, counter 13-1, which is included in the signal generating circuit 13, counts the reference clock signal outputted from the VCO 12, generates the system clock signal SCLK, and also generates the system signals MFP, FP by using the system clock signal SCLK. Additionally, the counter 23-1, which is included in the signal generating circuit 23, counts the reference clock signal outputted from the VCO 22, generates the system clock signal SCLK, and also generates the system signals MFP, FP by using the system clock signal SCLK. Here, the counters 13-1, 23-1 are reset by a carrier value internally generated.
The buffers 14, 24 separately and temporarily store the system clock signal SCLK and the system signals MFP, FP outputted from the signal generating circuit 13, 23. When outputs of the two buffers 14, 24 are provided to the system 30 at the same time, it causes the signals to collide. Thus, the outputs of the buffers 14, 24 are controlled by using the converting control signal ACT. That is, when the buffer 14 outputs the signals SCLK, MFP, and FP, an output of the buffer 24 is controlled so as to be tri-state. On the other hand, when the buffer 24 outputs the signals SCLK, MFP, and FP, an output of the buffer 14 is controlled so as to be tri-state. Collisions of the signals can thus be prevented.
As a result, if the first and second clock signal generators 10, 20 are converted by the converting control signal ACT, the related art system 30 can stably perform synchronization of the signals in an emergency situation.
The related art first and second clock signal generators 10, 20 perform synchronization in accordance with the reference clock signal of the whole system. However, a rate of the reference clock signal of the whole system is lower than the output signal of the VCO. Thus, when synchronization between the first and second clock signal generators 10, 20 is performed in accordance with a reference clock signal of the whole system, a phase difference between the first and second clock signal generator 10, 20 may be bigger than half a cycle of the VCO output.
In addition, the first and second clock generators 10, 20 separately generate signals required for the system by using separate VCOs. Thus, the timing synchronization of the system clock signal outputted from the first clock generator is different than that of the system clock signal outputted from the second clock generator.
Also, the related art signal generating circuit generates the system clock signal SCLK by using the output of the VCO and then generates the system signals MFP, FP by using the counter.
As depicted in FIG. 4, the phase of the system signals MFP, FP outputted from the first and second clock signal generator 10, 20 is also different than each other, because a reset timing of the counter included in the each signal generating circuit is different.
Accordingly, in the related art clock signal converting apparatus of the transmission system, when the conversion is performed from the first clock signal generator to the second clock signal generator, a system error occurs due to a synchronization discordance of the signal, i.e. the system clock signal and the system signal. Further, the error causes damage to a service provided by the system.
The above references are incorporated by reference herein where appropriate for appropriate teachings of additional or alternative details, features and/or technical background.
An object of the invention is to solve at least the above problems and/or disadvantages and to provide at least the advantages described hereinafter.
Another object of the present invention is to provide a clock signal converting apparatus of a transmission system that substantially obviates one or more problems caused by the disadvantages of the related art.
Another object of the present invention is to provide a stable system clock signal and system signal.
Another object of the present invention to to prevent a system error generated during conversion of a clock generator by synchronizing the two clock signal generators. It is another object of the present invention to provide a network synchronization by providing stable system clock signals and system signals.
To achieve at least these objects in whole or in parts, there is provided a clock signal converting apparatus of a transmission system having a first and a second clock signal generator, which separately generate various signals required for a system, the second clock signal generator is synchronized to the reference clock signal outputted from a VCO of the first clock signal generator in conversion of clock signal generator.
To achieve at least these objects in whole or in parts, there is further provided a clock signal converting apparatus of a transmission system that uses an output signal of the first clock signal as a reset signal of a counter included in the second clock signal generator in conversion of the clock generator.
Additional advantages, objects, and features of the invention will be set forth in part in the description which follows and in part will become apparent to those having ordinary skill in the art upon examination of the following or may be learned from practice of the invention. The objects and advantages of the invention may be realized and attained as particularly pointed out in the appended claims.